In many electronic devices, communication plays an important role regardless of the function these electronic devices fulfill. Most modern electronic devices contain integrated circuits (“IC”) containing circuitry on a silica component, for example, that exchange information with one another. An example is the communication between a processor and memory.
Often it is not possible to integrate all required functionality of an electronic device into a single IC, either because of the overall system complexity, or because different IC processes are required to implement the different functionalities. As an example, processors are typically manufactured using a different IC process than that used for memory devices, with each of these IC processes being highly optimized for its particular application.
The transfer of information from one silicon component to another is referred to herein as “chip-to-chip communications.” In chip-to-chip communications, silicon components may be connected by wires. Multiple such wires constitute a communication bus. A wire is considered as a path connecting two silicon components and may include elements such as die bonding pads, bumps, and bond wires, as well as circuit board pads, traces, and vias. Other embodiments may include passive components such as coupling capacitors and termination resistors in the chip-to-chip interconnection path.
In general, one would like chip-to-chip communications to be very reliable. Error rates on the order of one error per 1012 bits transmitted, or even lower, are typically required. Furthermore, the power consumption of the circuitry used for communicating has to be low. It is difficult to achieve both low-power and reliable communication goals. A certain amount of power is required to maintain signal integrity. Signal integrity may be degraded since wires may not be ideal, leading to signal distortion, attenuation, and interference.
A key parameter that influences signal integrity is the length of the wires. Long wires attenuate signals more and degrade the quality of the signals. Fundamentally, more power is required to drive longer wires.
A solution to the signal integrity problem is to bring the silicon components closer together. This would shorten the path between the silicon components and improve signal integrity and power consumption. Integrating both components on the same die would minimize the distance. However, because of cost and yield issues it is not always possible to integrate all components on the same die. Solutions that allow the length of inter-chip communication wires to be shortened include carefully designed printed circuit boards, package-on-package multi-chip configurations, and die-to-die interconnections using techniques such as through silicon vias (TSVs).
FIG. 1 is an example of a known chip-to-chip communication system, based on a printed circuit board 110 on which a processor 100, a memory device 120 and a memory device 130 are mounted. The processor 100 may communicate with memory device 120 by the wires 122 and with memory device 130 by the wires 124. The disadvantage of the architecture exemplified in FIG. 1 is that it is difficult to shorten the length of the wires to improve the signal integrity and lower the power consumption.
FIG. 2 shows an example of how multichip packaging may be used to reduce the length of signal paths such as those of FIG. 1. A first memory die 220 may be mounted on top of package substrate 210. The connection from memory die 220 to package bumps 240 comprises bondwires 230 and package trace 231. A second memory die 222 is mounted on top of memory die 220. The connection from memory die 222 to package bumps 240 comprises bondwires 232 and package trace 233.
Although integrating multiple dies into the same package as is illustrated in FIG. 2 is beneficial, some problems remain. First, the cost of a package as illustrated in FIG. 2 is more expensive than integrating a single die in a package. Second, although signal paths are much shorter than those of the previous figure, bondwires 230, 232 have a parasitic inductance that may induce crosstalk, and package traces 231, 233 and bumps 240 may introduce an additional loss in signal integrity.
To bring the processor still closer to the memory dies, one can opt for a package-on-package (“PoP”) design as exemplified in FIG. 3. FIG. 3 shows a processor die 312 that is mounted on a first package 310. Two memory dies 322 are mounted on a second package 320. The second package 320 is mounted on top of the first package 310 and the connection is made through bumps 330. The advantage of the configuration shown in FIG. 3 is that the path from memory devices 322 to processor die 312 is substantially shortened. However, there are still disadvantages to this package-on-package configuration. First, the costs of the full package are increased substantially, as the process of wire-bonding multiple dies is not easy. Second, the bond wires may still pose a challenge for signal integrity, with crosstalk still capable of degrading signals transmitted from memory dies 322 to processor die 312 and vice versa.
Another technology to combine multiple dies into a single package is the use of through-silicon vias. FIG. 4 shows an example of a package 410 on which a processor die 420 is mounted. Memory dies 430, 432 are mounted on top of the processor die 420. The conductive connection between processor die 420 and memory dies 430, 432 is made with through-silicon via (“TSV”) 440. Memory die 430 is connected to memory dies 432 by through-silicon vias 442 (and also by TSV 440 in some cases). One advantage of through-silicon vias is that the path between processor die 420 and the memory dies is substantially shortened. The use of through-silicon vias is known to have several disadvantages. First, the cost of the process to make through-silicon vias is very high, and the complexity of the process is such that it is very difficult to obtain high production yields. Second, there is low tolerance to misalignments of the individual dies. Third, such a direct non-flexible mechanical connection between dies will undergo shear stress when the two dies undergo differential thermal expansion, possibly to the point of destruction.
An alternative to TSVs is to couple two dies in a capacitive manner. FIG. 5 exemplifies a package 510 on which a processor die 520 is mounted. On top of processor die 520, a memory die 530 is mounted. Processor die 520 comprises a metal plate 540 and memory die 530 comprises a metal plate 542. The two metal plates 540, 542 are separated by a dielectric 544 and thus form a capacitor. A voltage induced on one of the capacitor plates 540, 542 may be sensed on the other plate. To provide sufficient coupling the distance between the two plates 540, 542 should be as small as possible. An advantage of capacitive coupling between chips is that mechanical stress between processor die 520 and memory die 530 is eliminated. A downside for capacitive coupling is that the two chips have to be mounted in a face-up/face-down manner to provide the necessary small distance between capacitor plates. That restricts the number of dies that can be stacked in this manner to two. Another downside of capacitive coupling is that the amount of power required for communications is relatively high.
An alternative to capacitive coupling is illustrated in FIG. 6. In FIG. 6, a package 610 contains a processor die 620 and two memory dies 630 and 632. Processor die 620 has an integrated inductor 640 that may be coupled to inductors 642, 643 that are integrated on memory dies 630, 632, respectively. The coupled inductors 640, 642 and 643 can be used to communicate between the different dies. An advantage of inductive coupling is that mechanical stress between dies is eliminated. There is more packaging flexibility than with capacitive coupling, as dies do not have to be mounted in a face-up/face-down manner, which allows stacking of more than two devices.
The disadvantage of inductive coupling has been acknowledged to be the amount of power required to achieve reliable communications over distances sufficiently large to support a large variety in die configurations. What is therefore needed are methods for communication between multiple dies that offer flexibility in die configurations and spacing, and that are very low power.